140 search results - page 3 / 28 » Optimization of high-performance superscalar architectures f... |
MICRO
2002
IEEE
13 years 11 months ago
2002
IEEE
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
AUTOID
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper presents a novel low power and high performance analog front end circuit for passive RFID transponder. With a novel architecture including three rectifier circuits, amo...
PDP
2009
IEEE
14 years 24 days ago
2009
IEEE
Abstract—Execution of applications on upcoming highperformance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will...
HPCA
2006
IEEE
14 years 6 months ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
ISCC
2005
IEEE
13 years 11 months ago
2005
IEEE
—A framework for designing a family of novel fast CRC generation algorithms is presented. Our algorithms can ideally read arbitrarily large amounts of data at a time, while optim...