4 search results - page 1 / 1 » Optimizing Issue Queue Reliability to Soft Errors on Simulta... |
ICPP
2008
IEEE
13 years 11 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
ISPASS
2007
IEEE
13 years 11 months ago
2007
IEEE
Semiconductor transient faults (i.e. soft errors) have become an increasingly important threat to microprocessor reliability. Simultaneous multithreaded (SMT) architectures exploi...
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
ISCA
2012
IEEE
11 years 7 months ago
2012
IEEE
Soft error reliability has become a first-order design criterion for modern microprocessors. Architectural Vulnerability Factor (AVF) modeling is often used to capture the probab...