17 search results - page 3 / 4 » Optimizing Nested Loops Using Local CPS Conversion |
IPPS
1996
IEEE
13 years 9 months ago
1996
IEEE
Minimizing communications when mapping affine loop nests onto distributed memory parallel computers has already drawn a lot of attention. This paper focuses on the next step: as i...
CC
2008
Springer
13 years 6 months ago
2008
Springer
The polyhedral model provides powerful abstractions to optimize loop nests with regular accesses. Affine transformations in this model capture a complex sequence of execution-reord...
IPPS
1999
IEEE
13 years 9 months ago
1999
IEEE
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
PLDI
2005
ACM
13 years 10 months ago
2005
ACM
A critical optimization in the domain of linear signal transforms, such as the discrete Fourier transform (DFT), is loop merging, which increases data locality and reuse and thus ...
PCI
2005
Springer
13 years 10 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...