12 search results - page 2 / 3 » Optimizing Reaching Definitions Overhead in Queue Processors |
ISCA
1996
IEEE
13 years 9 months ago
1996
IEEE
Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, ...
NIPS
2004
13 years 6 months ago
2004
We describe an algorithm for support vector machines (SVM) that can be parallelized efficiently and scales to very large problems with hundreds of thousands of training vectors. I...
TVLSI
2002
13 years 4 months ago
2002
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
CAL
2007
13 years 4 months ago
2007
—Several recently proposed techniques including CPR (Checkpoint Processing and Recovery) and NoSQ (No Store Queue) rely on reference counting to manage physical registers. Howeve...
ICS
1998
Tsinghua U.
13 years 9 months ago
1998
Tsinghua U.
In this paper we propose and evaluate the Adaptive++ technique, a novel runtime-only data prefetching strategy for software-based distributed shared-memory systems (software DSMs)...