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» Optimizing Test Length for Soft Faults in DRAM Devices
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VTS
2007
IEEE
71views Hardware» more  VTS 2007»
9 years 5 months ago
Optimizing Test Length for Soft Faults in DRAM Devices
: Soft faults in DRAMs are faults that do not get sensitized directly after an operation is performed, but require a time to pass before the fault can be detected. Tests developed ...
Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
9 years 3 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
ISQED
2002
IEEE
203views Hardware» more  ISQED 2002»
9 years 4 months ago
Automatic Test Program Generation from RT-Level Microprocessor Descriptions
The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach based on the generation of a test program. The proposed method relies on two p...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
SOCO
2010
Springer
8 years 5 months ago
Taximeter verification with GPS and soft computing techniques
Until recently, local governments in Spain were using machines with rolling cylinders for verifying taximeters. However, the condition of the tires can lead to errors in the proces...
José Villar, Adolfo Otero, José Oter...
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