6 search results - page 1 / 2 » Optimizing high speed arithmetic circuits using three-term e... |
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
Carry Save Adder (CSA) trees are commonly used for high speed implementation of multi-operand additions. We present a method to reduce the number of the adders in CSA trees by ext...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
The simulation of on-chip inductance using PEEC-based circuit analysis methods often requires the solution of a subproblem where an extracted inductance matrix must be multiplied ...
ARITH
2009
IEEE
13 years 11 months ago
2009
IEEE
Moduli of the form 2n ± 1, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs fo...
GLVLSI
2003
IEEE
13 years 9 months ago
2003
IEEE
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...