1990 search results - page 1 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
TC
1998
13 years 4 months ago
1998
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
CONCURRENCY
2006
13 years 5 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
SIGMOD
2004
ACM
14 years 5 months ago
2004
ACM
As more and more query processing work can be done in main memory, memory access is becoming a significant cost component of database operations. Recent database research has show...
IISWC
2008
IEEE
13 years 11 months ago
2008
IEEE
Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previou...
IPCCC
2006
IEEE
13 years 11 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...