7 search results - page 2 / 2 » Optimum Modulo Schedules for Minimum Register Requirements |
ISSS
2002
IEEE
13 years 10 months ago
2002
IEEE
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
DATE
2006
IEEE
13 years 9 months ago
2006
IEEE
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...