138 search results - page 1 / 28 » PADded Cache: A New Fault-Tolerance Technique for Cache Memo... |
VTS
1999
IEEE
13 years 8 months ago
1999
IEEE
This paper presents a new fault-tolerance technique for cache memories. Current fault-tolerance techniques for caches are limited either by the number of faults that can be tolera...
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
CASES
2009
ACM
13 years 7 months ago
2009
ACM
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
DSN
2005
IEEE
13 years 6 months ago
2005
IEEE
The increasing transient fault rate will necessitate onchip fault tolerance techniques in future processors. The speed gap between the processor and the memory is also increasing,...