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FCCM
1998
IEEE
113views VLSI» more  FCCM 1998»
13 years 8 months ago
PAM-Blox: High Performance FPGA Design for Adaptive Computing
PAM-Blox are object-oriented circuit generators on top of the PCI Pamette design environment, PamDC. High- performance FPGA design for adaptive computing is simplified by using a ...
Oskar Mencer, Martin Morf, Michael J. Flynn
CAMP
2000
IEEE
13 years 8 months ago
An FPGA Architecture for High Speed Edge and Corner Detection
This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per sec...
Cesar Torres-Huitzil, Miguel Arias-Estrada
IPPS
2006
IEEE
13 years 9 months ago
A stochastic multi-objective algorithm for the design of high performance reconfigurable architectures
The increasing demand for FPGAs and reconfigurable hardware targeting high performance low power applications has lead to an increasing requirement for new high performance reconf...
Wing On Fung, Tughrul Arslan
FPGA
1997
ACM
149views FPGA» more  FPGA 1997»
13 years 7 months ago
Signal Processing at 250 MHz Using High-Performance FPGA's
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
Brian Von Herzen
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
13 years 9 months ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar