Sciweavers

358 search results - page 71 / 72
» Parallel Evaluation Strategies for Functional Logic Language...
Sort
View
CODES
2005
IEEE
13 years 11 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
LCTRTS
2007
Springer
13 years 11 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
CGO
2010
IEEE
14 years 5 days ago
Automatic creation of tile size selection models
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...
Tomofumi Yuki, Lakshminarayanan Renganarayanan, Sa...
QNS
1996
13 years 6 months ago
Real Inferno
Inferno is an operating system well suited to applications that need to be portable, graphical, and networked. This paper describes the fundamental oating point facilities of the...
Eric Grosse
SSDBM
2003
IEEE
83views Database» more  SSDBM 2003»
13 years 10 months ago
PiQA: An Algebra for Querying Protein Data Sets
Life science researchers frequently need to query large protein data sets in a variety of different ways. Protein data sets have a rich structure that includes its primary structu...
Sandeep Tata, Jignesh M. Patel