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IPPS
1994
IEEE
13 years 8 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
IPPS
1998
IEEE
13 years 8 months ago
PACE: Processor Architectures for Circuit Emulation
We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circ...
Reiner Kolla, Oliver Springauf
IPPS
2008
IEEE
13 years 10 months ago
Adaptive and dynamic intrusion detection by means of idiotypic networks paradigm
—In this paper we present a novel intrusion detection architecture based on Idiotypic Network Theory (INIDS), that aims at dealing with large scale network attacks featuring vari...
Marek Ostaszewski, Pascal Bouvry, Franciszek Sered...
NPC
2004
Springer
13 years 9 months ago
Accurate Emulation of Wireless Sensor Networks
Abstract. Wireless sensor networks (WSNs) have a wide range of useful, datacentric applications, and major techniques involved in these applications include in-network query proces...
Hejun Wu, Qiong Luo, Pei Zheng, Bingsheng He, Lion...
HPCN
1997
Springer
13 years 8 months ago
Performance Evaluation of HPCN Applications
The performance attained by parallel programs executed on multiprocessor systems is largely in uenced both by the characteristics of the code and by those of the system architectu...
Alessandro P. Merlo