26 search results - page 5 / 6 » Parallel Hardware Architectures for the Cryptographic Tate P... |
CLUSTER
2009
IEEE
14 years 1 months ago
2009
IEEE
Abstract—In this paper we focus on optimizing the performance in a cluster of Simultaneous Multithreading (SMT) processors connected with a commodity interconnect (e.g. Gbit Ethe...
IPPS
2000
IEEE
13 years 10 months ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
ICCAD
2001
IEEE
14 years 3 months ago
2001
IEEE
Tight data- and timing constraints are imposed by communication and multimedia applications. The architecture for the embedded processor imply resource constraints. Instead of ran...
HPCA
2006
IEEE
14 years 6 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
CF
2010
ACM
13 years 9 months ago
2010
ACM
: The SpiNNaker machine is a massively parallel computing system, consisting of 1,000,000 cores. From one perspective, it has a place in Flynns' taxonomy: it is a straightforw...