63 search results - page 1 / 13 » Parallel algorithms for inductance extraction of VLSI circui... |
IPPS
2006
IEEE
13 years 10 months ago
2006
IEEE
IPPS
2002
IEEE
13 years 9 months ago
2002
IEEE
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is do...
HIPC
2004
Springer
13 years 10 months ago
2004
Springer
Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
IPPS
2006
IEEE
13 years 10 months ago
2006
IEEE
Models of simulation program with integrated circuit emphasis (SPICE) are currently playing a central role in the connection between circuit design and chip fabrication communitie...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...