2 search results - page 1 / 1 » Parametric yield in FPGAs due to within-die delay variations... |
FPGA
2007
ACM
13 years 11 months ago
2007
ACM
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
FPGA
2007
ACM
13 years 11 months ago
2007
ACM
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...