Sciweavers

26 search results - page 4 / 6
» Part I: buffer sizes for core routers
Sort
View
SBCCI
2005
ACM
276views VLSI» more  SBCCI 2005»
13 years 11 months ago
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...
Aline Mello, Leonel Tedesco, Ney Calazans, Fernand...
INFOCOM
2012
IEEE
11 years 8 months ago
A comparative study of architectural impact on BGP next-hop diversity
—Large ISPs have been growing rapidly in both the size and global connectivity. To scale with the sheer number of routers, many providers have replaced the flat full-mesh iBGP c...
Jong Han Park, Pei-chun Cheng, Shane Amante, Doria...
ICCCN
2008
IEEE
14 years 6 days ago
Work-Conserving Fair-Aggregation with Rate-Independent Delay
—Flow aggregation has been proposed as a technique to improve the scalability of QoS scheduling in the core of the Internet, by reducing the amount of per-flow state necessary a...
Jorge Arturo Cobb
ISPASS
2009
IEEE
14 years 17 days ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
GECCO
2006
Springer
191views Optimization» more  GECCO 2006»
13 years 9 months ago
The Brueckner network: an immobile sorting swarm
In many industrial applications, the dynamic control of queuing and routing presents difficult challenges. We describe a novel ant colony control system for a multiobjective sorti...
William A. Tozier, Michael R. Chesher, Tejinderpal...