24 search results - page 1 / 5 » Partial Error Masking to Reduce Soft Error Failure Rate in L... |
DFT
2003
IEEE
13 years 9 months ago
2003
IEEE
A new methodology for designing logic circuits with partial error masking is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic cir...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...
VLSID
2009
IEEE
14 years 5 months ago
2009
IEEE
We analyze the neutron induced soft error rate (SER). An induced error pulse is modeled by two parameters, probability of occurrence and probability density function of the pulse ...
ISQED
2010
IEEE
13 years 9 months ago
2010
IEEE
We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse widt...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...