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» Partial-Order Reduction in Symbolic State Space Exploration
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FPL
1999
Springer
147views Hardware» more  FPL 1999»
13 years 10 months ago
Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs
This paper details the development, implementation, and results of Synthia, a system for the synthesis of Finite State Machines (FSMs) to field-programmable logic. Our approach us...
George A. Constantinides, Peter Y. K. Cheung, Wayn...
IR
2008
13 years 5 months ago
A compressed self-index using a Ziv-Lempel dictionary
A compressed full-text self-index for a text T , of size u, is a data structure used to search for patterns P, of size m, in T , that requires reduced space, i.e. space that depend...
Luís M. S. Russo, Arlindo L. Oliveira
TASE
2007
IEEE
14 years 19 hour ago
Evaluation of SAT-based Bounded Model Checking of ACTL Properties
Bounded model checking (BMC) based on SAT has been introduced as a complementary method to BDD-based symbolic model checking of LTL and ACTL properties in recent years. For genera...
Yanyan Xu, Wei Chen, Liang Xu, Wenhui Zhang
SPIN
2000
Springer
13 years 9 months ago
Verification and Optimization of a PLC Control Schedule
Abstract. We report on the use of model checking techniques for both the verification of a process control program and the derivation of optimal control schedules. Most of this wor...
Ed Brinksma, Angelika Mader
MOBIHOC
2009
ACM
14 years 6 months ago
Delay and effective throughput of wireless scheduling in heavy traffic regimes: vacation model for complexity
Distributed scheduling algorithms for wireless ad hoc networks have received substantial attention over the last decade. The complexity levels of these algorithms span a wide spec...
Yung Yi, Junshan Zhang, Mung Chiang