28 search results - page 2 / 6 » Partitioned Schedules for Clustered VLIW Architectures |
EMSOFT
2006
Springer
13 years 9 months ago
2006
Springer
Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. ...
MICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
SPE
2008
13 years 5 months ago
2008
CF
2004
ACM
13 years 11 months ago
2004
ACM
Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The conse...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power mo...