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» Patchable instruction ROM architecture
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CASES
2001
ACM
13 years 8 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder
ICCD
1999
IEEE
115views Hardware» more  ICCD 1999»
13 years 9 months ago
Customization of a CISC Processor Core for Low-Power Applications
This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully util...
You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong...
ICCD
2006
IEEE
140views Hardware» more  ICCD 2006»
14 years 1 months ago
Clustering-Based Microcode Compression
Abstract— Microcode enables programmability of (micro) architectural structures to enhance functionality and to apply patches to an existing design. As more features get added to...
Edson Borin, Mauricio Breternitz Jr., Youfeng Wu, ...
VLSID
2001
IEEE
144views VLSI» more  VLSID 2001»
14 years 5 months ago
Next Generation Network Processors
Networking hardware manufacturers face the dual demands of supporting ever increasing bandwidth requirements, while also delivering new features, such as the ability to implement ...
Deepak Kataria
PLDI
1999
ACM
13 years 9 months ago
Enhanced Code Compression for Embedded RISC Processors
This paper explores compiler techniques for reducing the memory needed to load and run program executables. In embedded systems, where economic incentives to reduce both ram and r...
Keith D. Cooper, Nathaniel McIntosh