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» Path Analysis and Renaming for Predicated Instruction Schedu...
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IJPP
2000
94views more  IJPP 2000»
13 years 3 months ago
Path Analysis and Renaming for Predicated Instruction Scheduling
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...
IEEEPACT
1999
IEEE
13 years 8 months ago
Predicated Static Single Assignment
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...
MICRO
2006
IEEE
107views Hardware» more  MICRO 2006»
13 years 3 months ago
Dataflow Predication
Predication facilitates high-bandwidth fetch and large static scheduling regions, but has typically been too complex to implement comprehensively in out-of-order microarchitecture...
Aaron Smith, Ramadass Nagarajan, Karthikeyan Sanka...
IEEEPACT
1998
IEEE
13 years 8 months ago
Dynamic Hammock Predication for Non-Predicated Instruction Set Architectures
Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However, certain branches are difficult to predic...
Artur Klauser, Todd M. Austin, Dirk Grunwald, Brad...
ICS
1999
Tsinghua U.
13 years 8 months ago
Classifying load and store instructions for memory renaming
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary ...