73 search results - page 13 / 15 » Path Compression in Timed Automata |
FCCM
1997
IEEE
13 years 9 months ago
1997
IEEE
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
PERCOM
2011
ACM
12 years 9 months ago
2011
ACM
—In this paper, we consider the problem of tracking fine-grained speeds variations of vehicles using signal strength traces from GSM enabled phones. Existing speed estimation te...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
KBSE
2000
IEEE
13 years 9 months ago
2000
IEEE
The majority of work carried out in the formal methods community throughout the last three decades has (for good reasons) been devoted to special languages designed to make it eas...
ASE
2005
13 years 5 months ago
2005
Techniques for efficiently evaluating future time Linear Temporal Logic (abbreviated LTL) formulae on finite execution traces are presented. While the standard models of LTL are i...