29 search results - page 2 / 6 » Path delay test compaction with process variation tolerance |
DAC
1996
ACM
13 years 8 months ago
1996
ACM
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
DATE
2008
IEEE
13 years 10 months ago
2008
IEEE
We present the implementation and analysis of a variation tolerant version of a switch-to-switch link in a NoC. The goal is to tolerate the effects of process variations on NoC ar...
DATE
2007
IEEE
13 years 10 months ago
2007
IEEE
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
ISQED
2007
IEEE
13 years 10 months ago
2007
IEEE
Abstract—A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected...
VTS
2007
IEEE
13 years 10 months ago
2007
IEEE
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...