209 search results - page 2 / 42 » Performance Enhancement of Network Devices with Multi-Core P... |
DSN
2007
IEEE
13 years 11 months ago
2007
IEEE
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
MOBISYS
2009
ACM
14 years 5 months ago
2009
ACM
Mobile devices are increasingly equipped with multiple network interfaces with complementary characteristics. In particular, the Wi-Fi interface has high throughput and transfer p...
ICDCS
1996
IEEE
13 years 9 months ago
1996
IEEE
This paper evaluates the bene t of adding a shared cache to the network interface as a means of improving the performance of networked workstations con gured as a distributed shar...
INFOCOM
1998
IEEE
13 years 9 months ago
1998
IEEE
We study the performance of TCP in an internetwork consisting of both rate-controlled and non-rate-controlled segments. A commonexample of such an environment occurs when the end ...
DSN
2009
IEEE
2009
IEEE
Processor reliability enhancement through compiler-directed register file peak temperature reduction
13 years 9 months ago
Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliab...