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HIPEAC
2011
Springer
12 years 5 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
TJS
2002
118views more  TJS 2002»
13 years 5 months ago
The MAGNeT Toolkit: Design, Implementation and Evaluation
Abstract-The current trend in constructing high-performance computing systems is to connect a large number of machines via a fast interconnect or a large-scale network such as the ...
Wu-chun Feng, Mark K. Gardner, Jeffrey R. Hay
PDPTA
2003
13 years 7 months ago
The Performance of Routing Algorithms under Bursty Traffic Loads
Routing algorithms are traditionally evaluated under Poisson-like traffic distributions. This type of traffic is smooth over large time intervals and has been shown not necessaril...
Jeonghee Shin, Timothy Mark Pinkston
RTAS
2007
IEEE
13 years 12 months ago
Full Duplex Switched Ethernet for Next Generation "1553B"-Based Applications
Over the last thirty years, the MIL-STD 1553B data bus has been used in many embedded systems, like aircrafts, ships, missiles and satellites. However, the increasing number and c...
Ahlem Mifdaoui, Fabrice Frances, Christian Fraboul
INFOCOM
2002
IEEE
13 years 10 months ago
Design of Wavelength Converting Switches for Optical Burst Switching
— Optical Burst Switching (OBS) is an experimental network technology that enables the construction of very high capacity routers, using optical data paths and electronic control...
Jeyashankher Ramamirtham, Jonathan S. Turner