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DATE
2000
IEEE
110views Hardware» more  DATE 2000»
13 years 10 months ago
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
Alper Demir, Peter Feldmann
RTCSA
2009
IEEE
14 years 14 days ago
PLL Based Time Synchronization in Wireless Sensor Networks
Abstract—Time synchronization is a key component in numerous wireless sensor network applications. Most of the current software based time synchronization approaches suffer from ...
Gang Zhou, Sachin Shetty, George Simms, Min Song
ISPASS
2009
IEEE
14 years 17 days ago
Machine learning based online performance prediction for runtime parallelization and task scheduling
—With the emerging many-core paradigm, parallel programming must extend beyond its traditional realm of scientific applications. Converting existing sequential applications as w...
Jiangtian Li, Xiaosong Ma, Karan Singh, Martin Sch...
CODES
2010
IEEE
13 years 3 months ago
Worst-case performance analysis of synchronous dataflow scenarios
Synchronous Dataflow (SDF) is a powerful analysis tool for regular, cyclic, parallel task graphs. The behaviour of SDF graphs however is static and therefore not always able to ac...
Marc Geilen, Sander Stuijk
CODES
2010
IEEE
13 years 3 months ago
A task remapping technique for reliable multi-core embedded systems
With the continuous scaling of semiconductor technology, the life-time of circuit is decreasing so that processor failure becomes an important issue in MPSoC design. A software so...
Chanhee Lee, Hokeun Kim, Hae-woo Park, Sungchan Ki...