212 search results - page 2 / 43 » Performance and power modeling in a multi-programmed multi-c... |
IJPP
2010
13 years 2 months ago
2010
Exploiting the full computational power of current hierarchical multiprocessor machines requires a very careful distribution of threads and data among the underlying non-uniform ar...
ICCCN
2007
IEEE
13 years 11 months ago
2007
IEEE
—The emergence of multi-processor, multi-threaded architectures (referred to as multi- architectures) facilitates the design of high-throughput request processing systems (e.g., ...
ICC
2009
IEEE
14 years 1 days ago
2009
IEEE
—We consider a new generation of COTS Software Routers (SRs), able to effectively exploit multi-Core/CPU HW platforms. Our main objective is to evaluate and to model the impact o...
PPOPP
2006
ACM
13 years 11 months ago
2006
ACM
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
ICASSP
2010
IEEE
13 years 5 months ago
2010
IEEE
Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient managem...