33 search results - page 5 / 7 » Performance of Graceful Degradation for Cache Faults |
ISCA
2012
IEEE
11 years 7 months ago
2012
IEEE
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
VTS
2011
IEEE
12 years 9 months ago
2011
IEEE
This paper proposes an adaptive multi-bit error correcting code for phase change memories that provides a manifold increase in the lifetime of phase change memories thereby making...
ANSS
2000
IEEE
13 years 9 months ago
2000
IEEE
Software systems are known to suffer from outages due to transient errors. Recently, the phenomenon of “software aging”, one in which the state of the software system degrades...
PRDC
2005
IEEE
13 years 11 months ago
2005
IEEE
An important issue in modern cache designs is bridging the gap between wire and device delays. This warrants the use of more regular and modular structures to mask wire latencies....
SIGCOMM
2009
ACM
13 years 11 months ago
2009
ACM
This paper presents BCube, a new network architecture specifically designed for shipping-container based, modular data centers. At the core of the BCube architecture is its serve...