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» Performance of Parallel Concatenated Coding Schemes
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EMSOFT
2005
Springer
13 years 11 months ago
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
Guilin Chen, Mahmut T. Kandemir
JNW
2008
173views more  JNW 2008»
13 years 5 months ago
Dominating Set Theory based Semantic Overlay Networks for Efficient and Resilient Content Distribution
Recently overlay networks have emerged as an efficient and flexible method for content distribution. An overlay network is a network running on top of another network, usually the ...
J. Amutharaj, S. Radhakrishnan
DAC
2002
ACM
14 years 6 months ago
Design of a high-throughput low-power IS95 Viterbi decoder
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
Xun Liu, Marios C. Papaefthymiou
HPDC
2009
IEEE
14 years 16 days ago
Maintaining reference graphs of globally accessible objects in fully decentralized distributed systems
Since the advent of electronic computing, the processors’ clock speed has risen tremendously. Now that energy efficiency requirements have stopped that trend, the number of proc...
Björn Saballus, Thomas Fuhrmann
DSN
2007
IEEE
14 years 3 days ago
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
Christopher LaFrieda, Engin Ipek, José F. M...