5 search results - page 1 / 1 » Performance-driven register insertion in placement |
ISPD
2004
ACM
13 years 9 months ago
2004
ACM
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
With continued aggressive process scaling in the subwavelength lithographic regime, resolution enhancement techniques (RETs) such as optical proximity correction (OPC) are an inte...
ICCAD
1995
IEEE
13 years 7 months ago
1995
IEEE
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
LCPC
2005
Springer
13 years 9 months ago
2005
Springer
Techniques for global register allocation via graph coloring have been extensively studied and widely implemented in compiler frameworks. This paper examines a particular variant â...
ICCD
2008
IEEE
13 years 10 months ago
2008
IEEE
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...