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CGO
2006
IEEE
13 years 11 months ago
Selecting Software Phase Markers with Code Structure Analysis
Most programs are repetitive, where similar behavior can be seen at different execution times. Algorithms have been proposed that automatically group similar portions of a program...
Jeremy Lau, Erez Perelman, Brad Calder
ICCAD
2005
IEEE
131views Hardware» more  ICCAD 2005»
14 years 2 months ago
Code restructuring for improving cache performance of MPSoCs
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
Guilin Chen, Mahmut T. Kandemir
TOOLS
2009
IEEE
13 years 12 months ago
Reusing and Composing Tests with Traits
Single inheritance often forces developers to duplicate code and logic. This widely recognized situation affects both business code and tests. In a large and complex application w...
Stéphane Ducasse, Damien Pollet, Alexandre ...
CGO
2005
IEEE
13 years 10 months ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
LCTRTS
1999
Springer
13 years 9 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...