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ICCAD
2003
IEEE
136views Hardware» more  ICCAD 2003»
14 years 1 months ago
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
SBACPAD
2008
IEEE
206views Hardware» more  SBACPAD 2008»
13 years 10 months ago
A High Performance Massively Parallel Approach for Real Time Deformable Body Physics Simulation
Single processor technology has been evolving across last decades, but due to physical limitations of chip manufacturing process, the industry is pursuing alternatives to sustain ...
Thiago S. M. C. de Farias, Mozart W. S. Almeida, J...
PADS
2006
ACM
13 years 10 months ago
SOAr-DSGrid: Service-Oriented Architecture for Distributed Simulation on the Grid
Simulation is a low cost alternative to experimentation on real-world physical systems. Grid technology enables coordinated use of and secure access to distributed computing resou...
Xinjun Chen, Wentong Cai, Stephen John Turner, Yon...
HPCC
2005
Springer
13 years 9 months ago
Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
Francisco J. Villa, Manuel E. Acacio, José ...
CONNECTION
2007
87views more  CONNECTION 2007»
13 years 4 months ago
Efficient architectures for sparsely-connected high capacity associative memory models
In physical implementations of associative memory, wiring costs play a significant role in shaping patterns of connectivity. In this study of sparsely-connected associative memory...
Lee Calcraft, Rod Adams, Neil Davey