1189 search results - page 1 / 238 » Pipeline Timing Analysis Using a Trace-Driven Simulator |
RTCSA
1999
IEEE
13 years 9 months ago
1999
IEEE
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
AINA
2007
IEEE
13 years 11 months ago
2007
IEEE
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
HICSS
1994
IEEE
13 years 9 months ago
1994
IEEE
The development of accurate trace-driven simulation models has become a key activity in the design of new high-performance computer systems. Tracedriven simulation is fast) enabli...
MMS
2008
13 years 4 months ago
2008
Due to the increasing deployment of conversational real-time applications like VoIP and videoconferencing, the Internet is today facing new challenges. Low end-to-end delay is a vi...
INFOCOM
1992
IEEE
13 years 8 months ago
1992
IEEE
The current Internet is based on a stateless (datagram) architecture. However, many recent proposals rely on the maintenance of state information within network routers, leading t...