Sciweavers

192 search results - page 3 / 39
» Pipelined FPGA Adders
Sort
View
DAC
2003
ACM
14 years 5 months ago
Compiler-generated communication for pipelined FPGA applications
In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation, targete...
Heidi E. Ziegler, Mary W. Hall, Pedro C. Diniz
FCCM
2008
IEEE
153views VLSI» more  FCCM 2008»
13 years 10 months ago
A SRAM-based Architecture for Trie-based IP Lookup Using FPGA
Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbal...
Hoang Le, Weirong Jiang, Viktor K. Prasanna
FPL
2004
Springer
93views Hardware» more  FPL 2004»
13 years 9 months ago
The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays
This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPG...
Steven J. E. Wilton, Su-Shin Ang, Wayne Luk
ARC
2006
Springer
154views Hardware» more  ARC 2006»
13 years 8 months ago
Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems
This paper presents a reconfigurable hardware architecture for Public-key cryptosystems. By changing the connections of coarse grain Carry-Save Adders (CSAs), the datapath provides...
Kazuo Sakiyama, Nele Mentens, Lejla Batina, Bart P...
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
13 years 9 months ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar