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» Pipelined Memory Shared Buffer for VLSI Switches
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INFOCOM
1998
IEEE
13 years 10 months ago
Dynamic Flow Switching, A New Communication Service for ATM Networks
This paper presents a new communication service for ATM networks that provides one-way, adjustable rate, on-demand communication channels. The proposed dynamic flow service is des...
Qiyong Bian, Kohei Shiomoto, Jonathan S. Turner
ISCA
1995
IEEE
118views Hardware» more  ISCA 1995»
13 years 9 months ago
The EM-X Parallel Computer: Architecture and Basic Performance
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Ha...
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 6 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
OSDI
2004
ACM
14 years 6 months ago
FFPF: Fairly Fast Packet Filters
FFPF is a network monitoring framework designed for three things: speed (handling high link rates), scalability (ability to handle multiple applications) and flexibility. Multiple...
Herbert Bos, Willem de Bruijn, Mihai-Lucian Criste...

Publication
309views
15 years 5 months ago
SOLE: Scalable On-Line Execution of Continuous Queries on Spatio-temporal Data Streams
This paper presents the Scalable On-Line Execution algorithm (SOLE, for short) for continuous and on-line evaluation of concurrent continuous spatio- temporal queries over data str...
Mohamed F. Mokbel, Walid G. Aref