95 search results - page 3 / 19 » Pipelining with Futures |
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
EUROPAR
2001
Springer
13 years 10 months ago
2001
Springer
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
SIGMOD
2005
ACM
14 years 6 months ago
2005
ACM
We describe an approach for pipelining nested data collections in scientific workflows. Our approach logically delimits arbitrarily nested collections of data tokens using special...
ACSD
2005
IEEE
13 years 11 months ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
ARITH
2005
IEEE
13 years 7 months ago
2005
IEEE
Hash functions are an important cryptographic primitive. They are used to obtain a fixed-size fingerprint, or hash value, of an arbitrary long message. We focus particularly on ...