10 search results - page 1 / 2 » Placement of 3D ICs with Thermal and Interlayer Via Consider... |
DAC
2007
ACM
14 years 5 months ago
2007
ACM
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
One of the biggest challenges in 3D stacked IC design is heat dissipation. Incorporating thermal vias is a promising method for reducing the temperatures of 3D ICs. The bonding st...
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via lo...
SLIP
2009
ACM
13 years 10 months ago
2009
ACM
As technology advances, 3D ICs are introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the...
ISPD
2005
ACM
13 years 9 months ago
2005
ACM
As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promi...