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EURODAC
1994
IEEE
120views VHDL» more  EURODAC 1994»
13 years 8 months ago
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can ...
Chung-Wen Albert Tsao, Andrew B. Kahng
ICCAD
1994
IEEE
90views Hardware» more  ICCAD 1994»
13 years 8 months ago
Low-cost single-layer clock trees with exact zero Elmore delay skew
We give the rst single-layer clock tree construction with exact zero skew according to the Elmore delay model. The previous Linear-Planar-DME method 11 guarantees a planar solutio...
Andrew B. Kahng, Chung-Wen Albert Tsao