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» Plug-and-Play Architectural Design and Verification
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VLSID
2008
IEEE
225views VLSI» more  VLSID 2008»
11 years 6 months ago
Formal Verification of a Public-Domain DDR2 Controller Design
This paper demonstrates a formal verificationplanning process and presents associated verification strategy that we believe is an essential (yet often neglected) step in an ASIC o...
Abhishek Datta, Vigyan Singhal
DAC
2009
ACM
10 years 10 months ago
Exploiting "architecture for verification" to streamline the verification process
A typical hardware development flow starts the verification process concurrently with RTL, but the overall schedule becomes limited by the effort required to complete all the nece...
Dave Whipp
DAC
2006
ACM
11 years 2 days ago
Use of C/C++ models for architecture exploration and verification of DSPs
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
David Brier, Raj S. Mitra
DAC
2006
ACM
11 years 2 days ago
SystemC transaction level models and RTL verification
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
Stuart Swan
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