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» Plug-and-Play Architectural Design and Verification
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DAC
2005
ACM
9 years 10 months ago
VLIW: a case study of parallelism verification
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Li...
ICSE
2007
IEEE-ACM
10 years 8 months ago
Plug-and-Play Architectural Design and Verification
Abstract. In software architecture, components represent the computational units of a system and connectors represent the interactions among those units. Making decisions about the...
Shangzhu Wang, George S. Avrunin, Lori A. Clarke
DAC
2009
ACM
10 years 2 months ago
Beyond verification: leveraging formal for debugging
The latest advancements in the commercial formal model checkers have enabled the integration of formal property verification with the conventional testbench based methods in the o...
Rajeev K. Ranjan, Claudionor Coelho, Sebastian Ska...
VLSID
2002
IEEE
149views VLSI» more  VLSID 2002»
10 years 8 months ago
Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study
Choosing the right methodology is a significant step towards successful VLSI designs. Traditional methodologies and tools are no longer adequate to handle large and complex design...
Sanjeev Patel
DAC
2002
ACM
10 years 9 months ago
A comparison of three verification techniques: directed testing, pseudo-random testing and property checking
This paper describes the verification of two versions of a bridge between two on-chip buses. The verification was performed just as the Infineon Technologies Design Centre in Bris...
Mike Bartley, Darren Galpin, Tim Blackmore
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