48 search results - page 10 / 10 » Points-to analysis using BDDs |
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
FMCAD
2004
Springer
13 years 10 months ago
2004
Springer
Most symbolic model checkers are based on either Binary Decision Diagrams (BDDs), which may grow exponentially large, or Satisfiability (SAT) solvers, whose time requirements rapi...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...