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» Polynomial Identity Testing for Depth 3 Circuits
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ASPDAC
2004
ACM
113views Hardware» more  ASPDAC 2004»
13 years 8 months ago
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
Chi-Chou Kao, Yen-Tai Lai
ECCC
2010
124views more  ECCC 2010»
13 years 5 months ago
Lower Bounds and Hardness Amplification for Learning Shallow Monotone Formulas
Much work has been done on learning various classes of "simple" monotone functions under the uniform distribution. In this paper we give the first unconditional lower bo...
Vitaly Feldman, Homin K. Lee, Rocco A. Servedio
STACS
2010
Springer
13 years 12 months ago
Weakening Assumptions for Deterministic Subexponential Time Non-Singular Matrix Completion
Kabanets and Impagliazzo [KI04] show how to decide the circuit polynomial identity testing problem (CPIT) in deterministic subexponential time, assuming hardness of some explicit ...
Maurice Jansen
ICML
2005
IEEE
14 years 5 months ago
Bayesian hierarchical clustering
We present a novel algorithm for agglomerative hierarchical clustering based on evaluating marginal likelihoods of a probabilistic model. This algorithm has several advantages ove...
Katherine A. Heller, Zoubin Ghahramani
STOC
2009
ACM
133views Algorithms» more  STOC 2009»
14 years 5 months ago
New direct-product testers and 2-query PCPs
The "direct product code" of a function f gives its values on all k-tuples (f(x1), . . . , f(xk)). This basic construct underlies "hardness amplification" in c...
Russell Impagliazzo, Valentine Kabanets, Avi Wigde...