Sciweavers

2 search results - page 1 / 1
» Post-synthesis sleep transistor insertion for leakage power ...
Sort
View
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
13 years 10 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
DAC
2003
ACM
14 years 4 months ago
Distributed sleep transistor network for power reduction
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
Changbo Long, Lei He