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» Power Aware Dividers in FPGA
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INFOCOM
2010
IEEE
13 years 4 months ago
Dynamic Power Allocation Under Arbitrary Varying Channels - The Multi-User Case
Abstract—We consider the power control problem in a timeslotted wireless channel, shared by a finite number of mobiles that transmit to a common base station. The channel betwee...
Niv Buchbinder, Liane Lewin-Eytan, Ishai Menache, ...
ASPLOS
2008
ACM
13 years 7 months ago
Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs
Extracting high-performance from the emerging Chip Multiprocessors (CMPs) requires that the application be divided into multiple threads. Each thread executes on a separate core t...
M. Aater Suleman, Moinuddin K. Qureshi, Yale N. Pa...
ANCS
2011
ACM
12 years 5 months ago
ReClick - A Modular Dataplane Design Framework for FPGA-Based Network Virtualization
Network virtualization has emerged as a powerful technique to deploy novel services and experimental protocols over shared network infrastructures. Although recent research has hi...
Deepak Unnikrishnan, Justin Lu, Lixin Gao, Russell...
DIGITALCITIES
2000
Springer
13 years 10 months ago
Digital City for Disaster Reduction - Development of Pictogram System for Disaster Management
The purpose of this study is to apply digital city concept for the development of a pictogram system for natural disaster reduction. Long lasting and tangible achievement of IDNDR ...
Haruo Hayashi, Satoshi Tanaka, Kazunori Urabe, Har...