1238 search results - page 1 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
HPCA
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper provides a background and rationale for some of the architecture and design decisions in the Cell processor, a processor optimized for compute-intensive and broadband r...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
CF
2006
ACM
13 years 8 months ago
2006
ACM
The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As...
ASAP
2007
IEEE
13 years 6 months ago
2007
IEEE
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
ARITH
2005
IEEE
13 years 10 months ago
2005
IEEE
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...