3 search results - page 1 / 1 » Power Estimation of System-Level Buses for Microprocessor-Ba... |
ICCD
1999
IEEE
13 years 8 months ago
1999
IEEE
CODES
2004
IEEE
13 years 8 months ago
2004
IEEE
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
MICRO
2007
IEEE
13 years 10 months ago
2007
IEEE
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...