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VLSISP
2008
129views more  VLSISP 2008»
12 years 3 months ago
Architecture and Evaluation of an Asynchronous Array of Simple Processors
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, O...
ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
12 years 9 months ago
Localized microarchitecture-level voltage management
— Diminishing voltage margins, coupled with power and temperature constraints, call for microarchitecture-level runtime mechanisms for voltage control. This paper describes a loc...
YongKang Zhu, David H. Albonesi
DATE
2007
IEEE
97views Hardware» more  DATE 2007»
12 years 9 months ago
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
Abbas Sheibanyrad, Ivan Miro Panades, Alain Greine...
ASYNC
2005
IEEE
112views Hardware» more  ASYNC 2005»
12 years 9 months ago
Request-Driven GALS Technique for Wireless Communication System
A Globally Asynchronous - Locally Synchronous (GALS) technique for application in wireless communication systems is proposed and evaluated. The GALS wrappers are based on a reques...
Milos Krstic, Eckhard Grass, Christian Stahl
ASYNC
2002
IEEE
115views Hardware» more  ASYNC 2002»
12 years 8 months ago
Point to Point GALS Interconnect
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
George S. Taylor, Simon W. Moore, Robert D. Mullin...
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