24 search results - page 2 / 5 » Power and Performance Evaluation of Globally Asynchronous Lo... |
VLSISP
2008
13 years 4 months ago
2008
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
— Diminishing voltage margins, coupled with power and temperature constraints, call for microarchitecture-level runtime mechanisms for voltage control. This paper describes a loc...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
ASYNC
2005
IEEE
13 years 10 months ago
2005
IEEE
A Globally Asynchronous - Locally Synchronous (GALS) technique for application in wireless communication systems is proposed and evaluated. The GALS wrappers are based on a reques...
ASYNC
2002
IEEE
13 years 9 months ago
2002
IEEE
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...