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JILP
2000
90views more  JILP 2000»
13 years 4 months ago
Speculative Updates of Local and Global Branch History: A Quantitative Analysis
In today's wide-issue processors, even small branch-misprediction rates introduce substantial performance penalties. Worse yet, inadequate branch prediction creates a bottlen...
Kevin Skadron, Margaret Martonosi, Douglas W. Clar...
PADS
2004
ACM
13 years 10 months ago
Conservative Synchronization of Large-Scale Network Simulations
Parallel discrete event simulation techniques have enabled the realization of large-scale models of communication networks containing millions of end hosts and routers. However, t...
Alfred Park, Richard M. Fujimoto, Kalyan S. Peruma...
VLSID
2010
IEEE
173views VLSI» more  VLSID 2010»
13 years 8 months ago
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
Mohammad Arjomand, Hamid Sarbazi-Azad
PATMOS
2005
Springer
13 years 10 months ago
Enhanced GALS Techniques for Datapath Applications
Abstract. Based on a previously reported request driven technique for Globally-Asynchronous Locally-Synchronous (GALS) circuits this paper presents two significant enhancements. Fi...
Eckhard Grass, Frank Winkler, Milos Krstic, Alexan...
HIPEAC
2007
Springer
13 years 10 months ago
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...
Sonia López, Steve Dropsho, David H. Albone...