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ISLPED
1998
ACM
67views Hardware» more  ISLPED 1998»
13 years 9 months ago
Power and performance tradeoffs using various caching strategies
R. Iris Bahar, Gianluca Albera, Srilatha Manne
DATE
2005
IEEE
132views Hardware» more  DATE 2005»
13 years 11 months ago
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...
Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylve...
IPPS
2007
IEEE
13 years 11 months ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
13 years 10 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
DAC
2010
ACM
13 years 3 months ago
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation
Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates systemlev...
Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li