734 search results - page 2 / 147 » Power balanced pipelines |
HPCA
2003
IEEE
14 years 6 months ago
2003
IEEE
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
1 - This paper presents an efficient design exploration environment for high-end core processors. The heart of the proposed design exploration framework is a two-level simulation e...
MICRO
2003
IEEE
13 years 11 months ago
2003
IEEE
The impact of pipeline length on both the power and performance of a microprocessor is explored both theoretically and by simulation. A theory is presented for a wide range of pow...
ICCD
2002
IEEE
14 years 2 months ago
2002
IEEE
A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed. The execution time will be increased but, if the m...
SYNASC
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper we apply integer programming (IP) based techniques to the problem of delay balancing in wave-pipelined circuits. The proposed approach considers delays, as well as f...